A superscalar processing system includes multiple execution units for simultaneously executing multiple instructions. In some processing systems, instructions are executable out-of-order relative to their programmed sequence within the instruction stream. Accordingly, instructions' results are not necessarily available in-order of the instructions' programmed sequence. Nevertheless, some of these processing systems are designed to write instructions' results back to architectural registers in-order of the instructions' programmed sequence.
For this reason, some processing systems include rename buffers for intermediately storing instructions' results until a suitable moment for writing the intermediately stored results back to architectural registers. Previous techniques have been developed for controlling a processing system's rename buffers to accommodate data dependencies between the executed instructions. Nevertheless, shortcomings of such previous techniques include relatively slow speed, high complexity, and large physical size of systems implementing the techniques. With slow speed, high complexity, and large physical size, such systems are poorly suited for use in advanced integrated circuit microprocessors.
Thus, a need has arisen for a processing system and method of operation, in which speed of a system for controlling rename buffers is increased relative to previous techniques. Also, a need has arisen for a processing system and method of operation, in which complexity of a system for controlling rename buffers is decreased relative to previous techniques. Further, a need has arisen for a processing system and method of operation, in which physical size of a system for controlling rename buffers is decreased relative to previous techniques. Moreover, a need has arisen for a processing system and method of operation, in which a system for controlling rename buffers is more suited for use in advanced integrated circuit microprocessors relative to previous techniques.